meeting date: 24 may 2005
attending: Arpad Muranyi, Donald Telian, Mike LaBonte, Barry Katz, Scott McMorrow, Ken Willis

We discussed Todd's AR to talk to get a conversation with Synopsys:
- No one knew for sure what the status of this is.
- Ken: would be surprised if Synopsys went for it:
   - It would take lot of editing.
   - What's the business case?
- Barry: hspice "will not happen".

We discussed whether to focus on extended SPICE or VerilogA
- Ken: What is our goal?
  - To facilitate behavioral modeling.
- Barry: There is political baggage if we choose a spice.
  - Spice would be best for SiSoft, but it will not fly.
  - Best to move forward with VerilogA
  - Focus on implementing Donald's macromodeling, not building blocks.
- Ken: The VerilogA approach is workable
  - But scary because it is different.
- Arpad: VerilogA equations are easy, deciding the feature set is tough
  - VerilogA will do everything but prev(x).
  - prev(x) gives node voltage from the previous iteration, regardless of
    timestep.
- Donald: Ian has said Mentor is OK with VerilogA
  - Arpad: Ian likes that better than extending spice

Discussion of VerilogA versions and string parameter passing
- Arpad: VerilogAMS 2.2 is required for string parameter passing
  - Older versions can include a file, but it's not elegant.
  - The IBIS specifies VerilogAMS 2.0.
  - Version 2.2 released nov 2004.
- Mike: The IBIS spec should not mandate a version
  - IBIS specifies a version so users know what software to install.
  - Circuit models are for flexibility - should be no restrictions.
- Donald: String parameters are not used for macromodels
- Mike: That's because the Cadence language has a special format for
    table data. VerilogA tables will require string passing.
- Arpad:
  - VerilogA allows arrays of ports.
  - This would help with sparam and vsource/isource elements,
    which would be allowed to have variable port counts.
- We looked at Macromodel.VerilogA:
  - EQ.txt has design data, is read in by the called module.
  - May not be possible to have file name passed in.
  - Multiple instantiations of the same module definition may
    require separate, independent definitions.
- Arpad: hardcoded E element format is not flexible enough
- Arpad: having success playing with Cadence AMS Designer.

What to present at DAC:
- Mike: show a pre-emphasis driver example.
- Barry: show built-in terminator example.
- Arpad has already done it.
- Barry: show something for which we have a spice example.
  - Replicate one of Donald's macromodels in VerilogA?
- We should emphasize templates, not building blocks.
- Arpad: could show VerilogA mm and spice mm side by side.
  - Ken: not a good idea, stick with VerilogA.
  - IBIS should be an enabler, not a dictator.
- Mike: Should we show a receiver model?
  - Barry: No, it has to map to what simulators can handle.
AR: Arpad will create a VerilogA example for next week.

Question about what happens if we do nothing?
- Arpad: Today I have to write for both vams and vhdl.

AR: All we will discuss title of paper by email